The present invention relates to fabrication processes for semiconductor devices, and more particularly, to a method of manufacturing semiconductor devices for providing the formation of tungsten plugs and polysilicon plugs, and for minimizing the step-height differences of intermediate insulating layers by etching thin films on the semiconductor substrate using a specific etching composition and spin etching method, and to an etching for manufacturing semiconductor devices, and semiconductor devices made by these processes.
Recently, with semiconductor devices becoming more highly-integrated, there is an increased demand for the fine pattern formation technology of semiconductor devices and the multi-layered structure of circuit distribution.
In other words, the surface structure of the semiconductor devices are becoming more complicated, and the step-height differences between layers can cause malfunctions in the fabrication process of semiconductor devices.
Among the various fabrication processing steps, photolithography is used to form a photoresist pattern on the semiconductor substrate by coating a wafer with photoresist, aligning the wafer and a pattern mask having circuit distributions, and carrying out an exposure process by irradiating the photoresist on the wafer with light shining through the mask.
In the conventional fabrication method, the relatively-large Critical Dimension and the low-layered structure of the semiconductor devices cause few problems. However, with the finer patterns used on semiconductor substrates these days, and their multilayered structures, it is more difficult to exactly focus between the upper position and the lower position of the step-height difference in the exposure process, so that the precise pattern formation is hard to achieve.
Therefore, in order to minimize the step-height difference, the planarization technology of wafers has become more important. Conventionally, xe2x80x9cpartial planarizationxe2x80x9d has been employed for the planarization of wafers, using such methods as SOG film deposition, Etch Back, or Reflow, etc., which do not address the above problems and furthermore, cause many additional problems. As a result, xe2x80x9cglobal planarizationxe2x80x9d called the Chemical Mechanical Polishing (CMP) method has been developed as a planarization process that operates throughout the whole surface of the wafer.
The CMP method planarizes the wafer surface by means of chemical and physical reaction, that is, by supplying a slurry as a thin film on a surface of the wafer having a pattern formed thereon, contacting the wafer with the polishing pad surface, causing a chemical reaction on the wafer surface, and simultaneously allowing the uneven wafer surface to be physically polished by rotating the wafer to achieve planarization.
The removal rate and the uniformity of planarization are important parameters in the CMP technology, and these are determined by the processing conditions of the CMP facility, slurry types, and polishing pad types, etc. In particular, the components, pH, and ion concentration of the slurry greatly affect the chemical reaction of the thin film.
The slurry is mainly divided into two types, oxide film slurry and metal film slurry. The oxide film slurry is alkali, and the metal film slurry is acidic.
In the case where silicon dioxide (SiO2) is planarized using an oxide film CMP process, the property of the silicon dioxide (SiO2) is changed into hydrophillic subject to H2O permeability by the reaction with alkali slurry. The water intruded into the silicon dioxide (SiO2) disconnects the connection chains of the silicon dioxide (SiO2). Then, the silicon dioxide (SiO2) is removed by the physical mechanism with the abrasive.
In the case of metal film CMP process, however, the chemical reaction on the surface of the metal film by oxidant inside the slurry creates a metal oxide film, and the metal oxide film is removed by the mechanical (physical) friction of the abrasive starting with the outermost layer of the uneven pattern.
FIG. 1 is a schematic diagram showing a conventional CMP apparatus for manufacturing semiconductor devices.
Referring to FIG. 1, the CMP apparatus comprises a polishing head 102, a polishing table 104, and a polishing pad 108. The CMP process is carried out on the polishing table 104. The polishing pad 108 is formed on the polishing table and holds a semiconductor substrate 100. A slurry is then supplied from a slurry supply line 106 and is used to polish the substrate 100. The polishing head 102 secures the substrate 100 to the polishing pad and is movable in a rotational direction.
In operation, the polishing pad 108 contacts with the semiconductor substrate 100. The semiconductor substrate 100 is then rotated by the polishing head 102, and the slurry is supplied on the grinding pad 108. The slurry and the surface of the semiconductor substrate 100 then react each other, which causes the substrate to be polished by the polishing pad 108.
FIGS. 2 to 7 are cross sectional views for manufacturing semiconductor devices in order to describe the conventional processing sequences of a tungsten plug formation. The tungsten plug portion and an align mark during the tungsten plug formation are shown simultaneously.
FIGS. 2 to 7 are divided into a cell portion (C) for the formation of the pattern element and a peripheral portion (P) for the formation of the align mark, etc.
First, as shown in FIG. 2, an oxide film 114 is formed as an insulator on a semiconductor substrate 110 having a plurality of local patterns 112 preformed apart from each other. The local pattern 112 can use a polysilicon pattern or a metal pattern as a conductive layer. The oxide film 114 is a silicon dioxide film (SiO2) formed by a conventional Chemical Vapour Deposition process. Phosphosilicate (PSG) or Borophosphosilicate (BPSG) is used as an insulating layer between the polysilicon pattern and the metal film. The oxide film 114 is formed on the align mark portion (not shown).
Then, as shown in FIG. 3, in the planarization step of the oxide film 114, the oxide film 114, which is uneven by the local pattern 112, is planarized using the CMP apparatus shown in FIG. 1.
Then, as shown in FIG. 4, in the formation of contact hole 116, the contact hole 116 is formed via a typical photolithography and etch process by coating the oxide film 114 with photoresist and exposing the local pattern 112 and the semiconductor substrate 110. At this time, contact holes for forming the align mark 118 are formed with a diameter bigger than that of the contact hole 116.
Then, as shown in FIG. 5, in the formation of a barrier metal film 120, a titanium/titanium nitride (Ti/TiN) film is formed on the contact hole 116 as a barrier metal film 120 before forming a tungsten film. The Ti film 120a is formed using a conventional sputtering method. The TiN film 120b is formed using a conventional sputtering or a Chemical Vapour Deposition (CVD) method, and is not limited to either one or the other method. The barrier metal film 120 reduces the contact resistance of the tungsten film, and improves the adhesiveness of the oxide film 114 and the tungsten film. In addition, during a later process for removing the tungsten film, the barrier metal film 120 is used as stopper layer. At this time, the barrier metal layer 120 can be formed on the align mark 118.
Then, as shown in FIG. 6, in the formation of tungsten film 122, a tungsten film 122 is formed on the oxide film 114 having a certain thickness burying the contact hole 116. At this time, the tungsten film 122 is formed inside the align mark 118. Since the align mark 118 has a bigger diameter than that of the contact hole 116 of the cell part, the align mark 118 is not buried with the tungsten film 122, but has its bottom and sidewalls covered.
Then, as shown in FIG. 7, in the removal of the tungsten film 122, the semiconductor substrate 110 having the tungsten film 122 formed thereon is fixed on the polishing head 102 of the CMP apparatus of the FIG. 1, and the polishing pad 108 comes in contact with the tungsten film 112 while the metal film slurry is supplied from the slurry supply line 106. The grinding head 102 is then rotated to remove the tungsten film 112 on the barrier metal film 120 such that the tungsten film 112 remains only inside the contact hole 116. At this time, the tungsten film 112 still remains on the bottom and sidewalls of the align mark 118. The remaining tungsten film 112 on the align mark 118 function as particles in the following process thereby reducing the aligning ability of the photolithography process.
The CMP process for the formation of the tungsten plug is essential for the highly-integrated semiconductor devices fabrication process, but the CMP process causes microscratches on the thin film through the CMP process according to the slurry or the polishing apparatus of the CMP process. Furthermore, the slurry still remains on the align mark at a thickness of 2 to 4 times of the diameter of the contact hole, and on the scribe line portions so that they function as a particle source in later processes, thereby deteriorating the alignability of the photolithography process.
The tungsten plug formation process should be always conducted after the planarization of the insulating layer. Therefore, later processing, and frequently-conducted tests result in increased expenses due to the wafer monitor and the exchange of the expensive facilities. The tests conducted may be, e.g., to prevent the decrease of the productivity and maintain the CMP processing quality.
In addition, the abrasion of the polishing apparatus and the high pressure applied by the polishing head on the wafer for polishing frequently causes the wafer being to polished to break.
Furthermore, the facility efficiency can be deteriorated because the polishing of dummy wafers required to readjust the processing conditions after the exchange of the facility takes a long time.
In addition, the dry each back process used during the formation of the tungsten plug increases the contact resistance and the electrical heating for transistors because of the electrical charge-up of plasma according to intricate patterns.
Therefore, a demand has arisen to develop a method to address the above problems, and to provide a processing method carried out with more ease and efficiency, and to improve productivity.
There is provided a method of manufacturing semiconductor devices including a formation process of a tungsten plug or a polysilicon plug that omits a planarization process of intermediate insulating layers, and preventing the occurrence of the micro-scratches on the surface and the increase of the contact resistance. There is also provided a formation process of insulating layers for minimizing the step-height difference of the pattern on a semiconductor substrate. These methods substantially obviate one or more of the problems caused by the limitations and the disadvantages of the related art.
Another object of the present invention is to provide an etching method and an etching composition for effectively etching a tungsten film, a polysilicon film and an oxide film in horizontal direction.
To achieve these and other advantages and in accordance with the purpose of the present invention as embodied and broadly described, a method of manufacturing semiconductor devices comprises the steps of forming an insulator film over a semiconductor substrate; forming one or more contact holes in the insulator film; forming a tungsten film over the insulating layer and in the one or more contact holes; and spin-etching the tungsten film using an etching composition to remove a portion of the tungsten film outside of the one or more contact holes.
The contact hole is formed on a certain conductive layer on a semiconductor substrate, or is formed directly on a semiconductor substrate.
The method further comprises a step of forming a barrier metal film on the semiconductor structure including the contact hole before forming a tungsten film on the semiconductor structure. Preferably, the barrier metal film is Ti, TiN, or Ti/TiN.
The etching composition comprises at least one oxidant selected from the group consisting of H2O2, O2, IO4xe2x88x92, BrO3, ClO3, S2O83xe2x88x921, KlO3, H5IO6, KOH, and HNO3, at least one enhancer selected from the group comprising HF, NH4OH, H3PO4, H2SO4, and HCl, and a buffer solution.
The etching composition comprises HNO3 as an oxidant and a 0.01 to 3.0 mole ratio of HF as an enhancer. Most preferably, the etching composition comprises HNO3 as an oxidant and a 0.05 to 2.0 mole ratio of HF as an enhancer.
The etch rate of the etching composition for the tungsten film is in the range of 400 to 9000 xc3x85/min.
The etching composition may also comprise H2O2 as an oxidant and a 0 to 30 mole ratio of NH4OH as an enhancer. In this case, the etching composition most preferably comprises H2O2 as an oxidant and a 0 to 15 mole ratio of NH4OH as an enhancer.
The etch rate of the etching composition for the tungsten film is in the range of 200 to 3000 xc3x85/min.
The processing temperature of the etching composition during the spin-etching step is in the range of 20 to 90xc2x0 C., and preferably, the spin etch is carried out by a spin-spray method.
The spray amount of the etching solution is in the range of 0.1 to 2.5l/min, and the boom swing of a nozzle for spraying the etching composition is in the range of xe2x88x9280 to 80.
The rotation speed of a spin chuck used in the spin-spray method is in the range of 200 to 5000 rpm.
Preferably, the spin-etch for the tungsten film is carried out with two steps.
Another method of manufacturing semiconductor devices is provided, comprising the steps of forming an insulator film over a semiconductor substrate; forming one or more contact holes in the insulator film; forming a tungsten film over the insulating layer and in the one or more contact holes; carrying out a first spin-etching of the tungsten film to remove 40 to 95% of the thickness of the tungsten film by using a first etching composition having a high etch rate; and carrying out a second spin-etching of the tungsten film to remove an additional portion of the tungsten film outside of the one or more contact holes, by using a second etching composition having a lower etch rate than the first etching composition.
In another aspect, a method of manufacturing semiconductor devices comprises the steps of forming an insulating layer film over a semiconductor substrate; forming one or more contact holes in the insulating layer; forming a polysilicon film over the insulating layer and in the one or more contact holes; and spin-etching the polysilicon film using an etching composition to remove a portion of the polysilicon film outside of the one or more contact holes.
The contact hole is formed on a certain conductive layer on a semiconductor substrate, or the contact hole is directly formed on a semiconductor substrate.
The etching composition comprises at least one oxidant selected from the group comprising H2O2, O2, IO4xe2x88x92, BrO3, ClO3, S2O8xe2x88x92, KlO3, H5IO6, KOH, and HNO3, at least one enhancer selected from the group comprising HF, NH4OH, H3PO4, H2SO4, and HCl, and a buffer solution.
The etching composition comprises HNO3 as an oxidant and a 0.001 to 2.0 mole ratio of HF as an enhancer. Most preferably, the etching composition comprises HNO3 as an oxidant and a 0.005 to 0.05 mole ratio of HF as an enhancer.
The etch rate of the etching composition is in the range of 1000 to 15000 xc3x85/min.
The processing temperature of the etching composition during the spin-etching step is in the range of from 20 to 90xc2x0 C., and preferably, the spin etch is carried out by a spin-spray method.
The spray amount of the etching solution is 0.1 to 2.5 l/min., and the boom swing of a nozzle for spraying the etching composition is in the range of xe2x88x9280 to 80.
The rotation speed of a spin chuck used in the spin-spray method is in the range of 200 to 5000 rpm.
A method of manufacturing semiconductor devices comprises the steps of forming a lower structure on a semiconductor substrate having lower height; forming an upper structure on a semiconductor substrate having an upper height greater than the lower height; forming a intermediate insulating layer over the upper and lower structures; and spin-etching the intermediate insulating layer using a etching composition to achieve planarization of the intermediate insulating layer, wherein a step height difference is equal to the difference between the upper and lower heights, and wherein the intermediate insulating layer is thicker than the step-height difference.
The intermediate insulating layer is an oxide film.
The etching composition comprises at least one oxidant selected from the group comprising H2O2, O2, IO4xe2x88x92, BrO3, ClO3, S2O8xe2x88x92, KlO3, H5IO6, KOH, and HNO3, at least one enhancer selected from the group comprising HF, NH4OH, H3PO4, H2SO4, and HCl, and a buffer solution.
The etching composition comprises HNO3 as an oxidant and a 0.01 to 3.0 mole ratio of HF as an enhancer. Most preferably, the etching composition comprises HNO3 as an oxidant and a 0.05 to 1.0 mole ratio of HF as an enhancer.
The etch rate of the etching composition is in the range of 1000 to 25000 xc3x85/min.
The processing temperature of the etching composition during the spin-etching step is in the range of 20 to 90xc2x0 C., and the spin etch is carried out by a spin-spray method.
Preferably, the spray amount of the etching solution is in the range of 0.1 to 2.5 l/min.
The boom swing of a nozzle for spraying the etching composition is in the range of xe2x88x9280 to 80, and the rotation speed of a spin chuck used in the spin-spray method is in the range of 200 to 5000 rpm.
An etching composition for manufacturing semiconductor devices comprises at least one oxidant selected from the group comprising H2O2, O2, IO4xe2x88x92, BrO3, ClO3, S2O8xe2x88x92, KlO3, H5IO6, KOH, and HNO3, at least one enhancer selected from the group comprising HF, NH4OH, H3PO4, H2SO4, and HCl, and a buffer solution.
The etched material is a tungsten film, a polysilicon film, or an oxide film, and the buffer solution is deionized water for controlling concentration, temperature and the resulting contact angle of the etching composition.
According to the present invention, an etching composition for manufacturing semiconductor devices for spin-etching a certain material on a semiconductor substrate comprises HNO3 as an oxidant and a 0.001 to 3.0 mole ratio of HF as an enhancer.
The etched material by the etching composition is a tungsten film, a polysilicon film, or an oxide film.
In another aspect, an etching composition of the present invention for manufacturing semiconductor devices for spin-etching a certain material on a semiconductor substrate comprises H2O2 as an oxidant and a 0 to 30 mole ratio of NH4OH as an enhancer.
The etched material by the etching composition is a tungsten film.
In another aspect, according to the present invention, a semiconductor device comprising a cell portion formed on a semiconductor substrate, having one or more metal film plugs formed in one or more contact holes to electrically connect a plurality of patterns; a peripheral portion surrounding the cell portion and including at least one align mark formed by the same formation method as the one or more contact holes; and an insulating layer formed over the cell portion and the peripheral portion.
Preferably, the metal film is a tungsten film.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.